1. Field of the Invention
This invention relates to integrated circuits, and in particular to a method for manufacturing integrated injection logic devices having self-aligned base contacts, and the resulting structure.
2. Prior Art
Integrated injection logic devices and circuits are known in the art and have been the subject of numerous patents and publications. See, e.g., U.S. Pat. No. 3,962,717 to O'Brien. This patent discloses an integrated injection logic (I.sup.2 L) device formed in an oxide isolated region of an epitaxial layer of semiconductor material. Also known is the use of boron doped polycrystalline silicon as a diffusion source for p-type regions of I.sup.2 L devices. See, e.g., "Polycrystalline Silicon as a Diffusion Source and Interconnect Layer in I.sup.2 L Realizations" by Middelhoek and Kooy, IEEE Journal of Solid State Circuits, Vol. SC-12, No. 2, April 1977.
Prior art I.sup.2 L circuits, however, suffer from certain disadvantages relating to speed, density, number of fan-outs permitted, and the crossing of such structures by metal interconnecting lines. One goal in designing injection logic structures is to maintain the resistance of the base region while increasing the beta of the transistor. In prior structures, this has been accomplished by scaling of the structure in a horizontal or vertical direction. At a certain point, however, scaling does not provide further improvements in beta because the p+ collar which surrounds the n+ collectors determines the base resistance and beta.